Technical Working Groups
Events
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2025 Q3 Core Member Meeting
August 27, 2025, 09:00-13:30
Grand Ballroom 1, 3rd Floor, East Wing, Sheraton Hsinchu Hotel
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Special Lecture: Next Gen Computing with UCIe
August 7, 2025, 09:00-11:00
Room 3A, 3F, Building 51, ITRI Chung Hsing Campus
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2025 Q2 Core Member Meeting
May 15, 2025, 09:30-13:30
Apollo III, B1, Leith Castle, Lakeshore Hotel Hsinchu
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2025 Q1 Core Member Meeting
March 13, 2025, 09:30-13:30
Grand Ballroom 1, 3rd Floor, East Wing, Sheraton Hsinchu Hotel
About Hi-CHIP
With the rapid development of advanced manufacturing processes, IC design cycle and cost have increased significantly. For example, the design cycle of 7 nanometers is twice that of 28 nanometers, the design cost is more than US $300 million, and the design cost of 5 nanometers will exceed US $500 million. As a result, the efficiency of the chip will fall into a slow growth trend. Therefore, multi-dimensional chip design and heterogeneous integrated packaging architecture will be the most important development path of semiconductors in the future. At the same time, AI and 5g detonate various emerging technology applications, facing different circuits in the same package
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