Backside Power Delivery Gears Up For 2nm Devices
- 發佈日期 : 2024-02-26
- 資料來源：Semiconductor Engineering
- 瀏覽人次：15
But this novel approach to optimizing logic performance depends on advancing lithography, etching, polishing, and bonding processes.
The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower noise across multiple metal layers.
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