Hi-CHIP 異質整合系統級封裝開發聯盟

Selective deposition could slow the need for additional lithography steps, helping to control costs for advanced-node chips.

Rising lithography costs, shrinking feature sizes, and the need for an alternative to copper are collectively spurring new interest in area-selective deposition. An extension of atomic layer deposition, ASD seeks to build circuit features from the bottom up, without relying on lithography.

詳見內文，請點選連結：【Sidestepping Lithography In Chip Manufacturing】