Floor-Planning Evolves Into The Chiplet Era
- 發佈日期 : 2024-07-31
- 資料來源：Semiconductor Engineering
- 瀏覽人次：15
Automatically mitigating thermal issues becomes a top priority in heterogeneous designs.
3D-ICs and heterogeneous chiplets will require significant changes in physical layout tools, where the placement of chiplets and routing of signals can have a big impact on overall system performance and reliability.