Hi-CHIP 異質整合系統級封裝開發聯盟

As connectivity increasingly defines the limits of AI system performance, this gathering will bring you deep insights into the evolution from SerDes to Co-Packaged Optics (CPO), examining multi-scale interconnect architectures from package to data center. Alongside this, we will explore Integrated Glass Waveguide innovations, Advanced Substrates for the AI Era, and Miniaturized SiP and Power Solutions in Advanced Packaging. We look forward to diving into these cutting-edge technical breakthroughs with you as we shape the next generation of high-performance computing and optical-electronic integration together.

This meeting is always a wonderful occasion to catch up with old friends, spark new ideas, and connect with fellow industry peers across the supply chain.

Meeting Information

Ÿ   Date: Friday, September 18, 2026

Ÿ   Time: 09:30–13:30 (Registration starts at 09:00)

Ÿ   Venue: Grand Ballroom 1, 3rd Floor, East Wing, Sheraton Hsinchu Hotel

Ÿ   Language: English

Ÿ   Agenda: