Defining Chip Threat Models To Identify Security Risks
- 發佈日期 : 2024-08-08
- 資料來源：https://semiengineering.com/defining-chip-threat-models-to-determining-security-risks/
- 瀏覽人次：13
Not every device has the same requirements, and even the best security needs to adapt.
Experts At The Table: As hardware weaknesses have become a major target for attackers, the race to find new ways to strengthen chip security has begun to heat up. But one-size does not fit all solution. To figure out what measures need to be taken, a proper threat model must be assessed. Semiconductor Engineering sat down with a panel of experts at the Design Automation Conference in San Francisco, which included Andreas Kuehlmann, CEO of Cycuity; Serge Leef, head of secure microelectronics at Microsoft; Lee Harrison, director of Tessent automotive IC solutions at Siemens EDA; Pavani Jella, vice president hardware security EDA solutions at Silicon Assurance (on behalf of IEEE P3164); Warren Savage, researcher at the University of Maryland’s Applied Research Lab for Intelligence and Security and is currently the Principal Investigator of the Independent Verification and Validation (IV&V) team for the Defense Advanced Research Projects Agency (DARPA) AISS program; Maarten Bron, managing director at Riscure/Keysight; Marc Witteman, CEO at Riscure/Keysight; Mike Borza, scientist at Synopsys; Farimah Farahmandi, Wally Rhines Endowed Professor in Hardware Security and Assistant Professor at the University of Florida, and co-founder of Caspia Technologies; and Mark Tehranipoor, chair of the ECE department at University of Florida, founder of Caspia Technologies. What follows are excerpts of that discussion.
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