Heterogeneous Integration and Chiplet System Package Alliance

With the rapid development of advanced manufacturing processes, the IC design cycle and cost have significantly increased. For example, the design cycle for 7nm is twice that of 28nm, with a design cost of over 300 million US dollars, and 5nm will exceed 500 million US dollars. As a result, the performance of chips has slowed down, and multidimensional chip design and heterogeneous integration packaging structures will be the most important development path for semiconductors in the future.

At the same time, AI and 5G are driving various emerging technology applications, and facing the demand for smaller signal paths, larger bandwidth, lower power consumption, thinner and smaller chip sizes, and finer pitch, signal/power integrity, thermal, integration, and cost control challenges between different circuits within the same package. Through heterogeneous integration, there is an opportunity to solve these challenges.

In view of this, ITRI, which has many years of experience in the development of heterogeneous integration technology, is not only continuously investing resources to strengthen the development of Fan-out, 2.5/3DIC, EIC, and SOIC technologies but also connecting with international alliances such as AITA, UCLA CHIPS, etc. In 2021, it officially co-established the "Hi-CHIP Heterogeneous Integration System-Level Packaging Development Alliance" with domestic and foreign semiconductor giants, providing AIOT system application platforms and shuttle services, building advanced packaging manufacturing process lines, starting from system applications, and developing forward-looking heterogeneous integration technologies as the process and testing equipment are gradually put in place. It also links with Taiwan's semiconductor industry chain to assist domestic and foreign startups in technical services from packaging design, testing and verification to small-scale production, and achieve the goal of localizing the supply chain.