Heterogeneous Integration and Chiplet System Package Alliance
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Technical Working Group
3D/FO Process Integration
Missions
．3D Chiplet Stack
．Fan-Out Pilot Line
．CPO Integration
R&D Planning
| 2023 | 2023-2025 | 2026-2028 |
|
Wafer Level Fan-out （2D Chiplet Integration） |
Reconstituted Wafer to Wafer （logic+ memory tiles） |
3D Chiplet Integration （CPO, Qubit, super TGP） |
Members of SIGs
．General Convener：Johnson Tai, General manager, Raytek
．Deputy Convener：Mike Chang, Manager, ITRI
Operation Mechanism
．Regular meeting：2 times a year