Floor-Planning Evolves Into The Chiplet Era
- Date : 2024-07-31
- Source：Semiconductor Engineering
- Views ：85
Automatically mitigating thermal issues becomes a top priority in heterogeneous designs.
3D-ICs and heterogeneous chiplets will require significant changes in physical layout tools, where the placement of chiplets and routing of signals can have a big impact on overall system performance and reliability.
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