Hi-CHIP 2026 Q3 Core Member Meeting
- Date : 2026-09-21
- Source：Heterogeneous Integration and Chiplet System Package Alliance
- Views ：34
- Event date
- September 18, 2026, 09:30-13:30
- Event Location
- Grand Ballroom 1, 3rd Floor, East Wing, Sheraton Hsinchu Hotel
- Organizer
- Hi-CHIP Alliance
As connectivity increasingly defines the limits of AI system performance, this gathering will bring you deep insights into the evolution from SerDes to Co-Packaged Optics (CPO), examining multi-scale interconnect architectures from package to data center. Alongside this, we will explore Integrated Glass Waveguide innovations, Advanced Substrates for the AI Era, and Miniaturized SiP and Power Solutions in Advanced Packaging. We look forward to diving into these cutting-edge technical breakthroughs with you as we shape the next generation of high-performance computing and optical-electronic integration together.
This meeting is always a wonderful occasion to catch up with old friends, spark new ideas, and connect with fellow industry peers across the supply chain.
Meeting Information
Date: Friday, September 18, 2026
Time: 09:30–13:30 (Registration starts at 09:00)
Venue: Grand Ballroom 1, 3rd Floor, East Wing, Sheraton Hsinchu Hotel
Language: English
Agenda:
|
Time |
Session |
|
09:00-09:30 |
Registration |
|
09:30-09:35 |
Opening Remarks |
|
09:35-10:05 |
From SerDes to Co-Packaged Optics: Connectivity Architectures for AI Compute |
|
10:05-10:35 |
Integrated Glass Waveguide Innovations for Next-Generation CPO |
|
10:35-10:55 |
Break |
|
10:55-11:25 |
The Trend of Advanced Substrate for AI Era |
|
11:25-11:55 |
Miniaturized SiP and Power Solutions in Advanced Packaging |
|
11:55-12:00 |
Closing Remarks |
|
12:00-13:30 |
Lunch |
